1. Field of the Invention
The invention relates to a clock and data recovery circuit and more particularly to a gated voltage-controlled oscillator.
2. Description of the Related Art
A CDR (Clock and Data Recovery) circuit is used to retrieve a clock signal synchronized with the phase of the input data and perform data regeneration according to phase synchronization information.
FIG. 1a is a block diagram of a CDR circuit 10 in prior arts. The CDR circuit 10 comprises an edge detector 110, a gated voltage-controlled oscillator (GVCO) 120, and a D flip-flop (DFF) 130. The edge detector 110 comprises a delayer 112, an exclusive-or (XOR) gate 114, and an inverter 116. The edge detector 110 receives input data DI and generates a gating signal GS which is synchronized with the ascending phase or the descending phase of the input data DI. The GVCO 120 performs instantaneous phase realignment according to the gating signal GS to oscillate a clock signal CLK corresponding to the input data DI. The DFF 130 receives the clock signal CLK from the GVCO 120 and recovers data from the input data DI to output recovered data DO.
FIG. 1b is an example of a waveform diagram of the CDR circuit 10 in FIG. 1a. The waveform 1 is the waveform of the input data DI. The waveform 2 is the output waveform of the delayer 112 in FIG. 1a by which the input data DI is delayed for T/2. The waveform 3 is the output waveform of the XOR gate 114. Pulses of the waveform 3 correspond to ascending or descending edges of the input data DI. The waveform 4, the waveform of the gating signal GS, is an inverse of the waveform 3. The waveform 5 is the output waveform of the GVCO 120 in FIG. 1a. That is, the waveform 5 is the waveform of the clock signal CLK.
FIG. 1c is a block diagram of the GVCO 120 in FIG. 1a. Typically, the GVCO 120 comprises an NAND gate 122 and inverters 124-1˜124-n. One input terminal of the NAND gate 122 receives the gating signal GS. The other input terminal is coupled to the output terminal of the GVCO 120. The output terminal of the NAND gate 122 is coupled to serially-connected inverters 124-1˜124-n. The serially-connected inverters 124-1˜124-n become a delay unit. FIG. 1d is an example of the circuit diagram of the NAND gate 122 in FIG. 1c. As shown in FIG. 1d, when the NAND gate 122 is operated, there is asymmetry.
Moreover, the output clock signal may have unnecessary jitter when the NAND gate is used to constitute the GVCO. For avoiding unnecessary jitter, the bandwidth of the NAND gate is usually increased. However, the bandwidth is limited in the normal CMOS manufacturing process. In addition, the operating current has to be increased when the bandwidth is increased, and thus the circuit area is enlarged.